1. Field of the Invention
The present invention relates to a back wiring board (BWB) wiring design system. More particularly, the present invention is concerned with a BWB transmission wiring design system and with a method capable of guaranteeing the super high-speed operation of an entire system composed of a BWB and a plurality of printed circuit boards mounted on the BWB.
2. Description of the Related Art
In recent years, a data transmission speed at which data is transmitted over a transmission line and the capacity of the transmission line have increased along with an increase in the traffic on a communication channel or an increase in a channel capacity. Communication systems are therefore required to operate at a high speed and handle a large amount of data. Regarding transmission on a back wiring board (BWB) incorporated in a communication system, it has become necessary to meet a demand for transmission on several thousands of channels at a speed of 3 Gbps, in recent years. Incidentally, transmission on hundreds of channels at a speed of 600 Mpbs is demanded conventionally.
In this case, the type of signals to be transmitted on a BWB is being changed from a conventional single-ended signal (a signal at a ground potential when it is at a zero level) to two differential-mode signals (a paired signal with positive and negative phases). This is attributable to such factors as adoption of an LSI that transmits signals over a long distance at a high speed and a trend to low power consumption. Thus, the number of signal lines has been doubled.
Consequently, a printed circuit board (PCB) must be designed in consideration of the length of a printed pattern, the number of via holes, a board material, values inherent to each part, and so on, so that a transmission loss and a delay time can be managed more strictly. On the other hand, conventionally, a signal speed to be attained on a BWB and a density of lines to be formed thereon need not be strictly managed. Moreover, a single-glass-epoxy material, for example, FR-4 may be adopted as a material to be made into a printed circuit board.
Therefore, only the length of a printed pattern in a plug-in unit (PIU) or the length of a printed pattern on a BWB should be managed in order to realize desired transmission characteristics. Designing is enabled when, for example, the length of the printed pattern in the PIU falls within a range of 100 mm±20 mm, and the length of the printed pattern on the BWB falls within a range of 800 mm±20 mm.
FIG. 1 shows an example of the structure of a conventional BWB.
Referring to FIG. 1, two PIUs 2 and 6 are plugged into a BWB 1 via sheet connectors 3 and 7 respectively. A pattern of single-ended lines capable of guaranteeing a signal transmission speed of 600 Mbps has been adopted in the past.
What is referred to as the pattern of single-ended lines is such that one signal wave is allocated to each signal line and one end of each signal line is connected to a common ground. For example, when signals to which several hundreds of channels are assigned are routed on the BWB 1, the BWB 1 is provided with a signal layer in which a pattern of lines 5 corresponding to several hundreds of channels is formed and a ground layer in which a common ground is formed.
Referring to FIG. 1, a transmission LSI 4 is mounted on the PIU 2, and a reception LSI 8 is mounted on the PIU 6. Consequently, the wiring for signal line is designed in consideration of line lengths permitted to lines extended between the transmission LSI 4 on the PIU 2 and the reception LSI 8 on the PIU 6.
FIG. 2 shows an example of a margin permitted to a parameter relevant to a system including a BWB and PIUs after conventional transmission wiring design.
Assuming that a signal is transmitted at a speed of 600 Mbps as it conventionally is, a transmission loss or a transmission delay time calculated from a permissible value specified in LSI device information concerning transceivers or the like installed at both a signal transmitting end and a signal receiving end is provided with a sufficient tolerance, that is, a large margin permitted after wiring design. The tolerance, that is, the margin is permitted to the transmission loss or delay time relative to a value that must be strictly observed in designing wiring to interconnect all parts including the BWB, PIUs 1 and 2, via holes (VIA), and connectors (CN).
FIG. 3 shows an example of a conventional transmission wiring design system.
As mentioned above, conventionally, a large margin is permitted after wiring design. Therefore, unique conditions for wiring can be set for each of the BWB and PIUs, and independent transmission wiring design systems 11 to 13 can be used to design wiring under the unique conditions for wiring. In this example, a line length of 100±20 mm is permitted to wiring design for each PIU, while a line length of 800±20 mm is permitted to wiring design for the BWB. The values of the line lengths are given a sufficient after-design margin. Even if a PIU is manufactured to deviate from the specifications determined therefor, no problem occurs in the whole of a system including the BWB and PIUs.
However, when a signal transmission speed on a BWB is equal to or larger than the level of giga bits per sec, not only the line lengths but also a transmission loss or delay time caused by via holes and a transmission loss or delay time caused by a connector must be taken account. When the line lengths are managed as they conventionally are, design cannot be achieved successfully.
Moreover, in order to minimize a loss to be undergone by high-frequency signal components, a material other than the conventionally adopted FR-4, for example, a low-dielectric material must be adopted. A loss or delay time per unit length of a printed pattern is therefore different from the conventional one. Management of wiring design then becomes harder.
FIG. 4 shows an example of the structure of a BWB on which signals are transmitted at 3 Gbps.
In this example, a line pair including two lines (for signals with positive and negative phases) is used to transmit one signal. Moreover, one system accommodates several thousands of channels in conformity with a recent demand for a large channel capacity and a compact design. In this case, the number of lines on the BWB is much larger than the conventional one. Wiring design itself becomes unfeasible as long as a conventional technique is adopted.
FIG. 5 and FIG. 6 show an example of a current margin permitted to a parameter relevant to a system including a BWB and PIUs after wiring design.
Assuming that signals are transmitted at 3 Gbps, the conventional margin permitted to wiring design as shown on the left side of FIG. 5 (identical to FIG. 2) is too insufficient to achieve the wiring design. Therefore, another material is adopted as a material of manufacture printed circuit boards, that is, a low-dielectric material, for example, LX is adopted.: Nevertheless, as shown on the right side of FIG. 5, a margin permitted after wiring design is nearly nil.
FIG. 6 shows an example of transmission losses caused by parts included in a BWB and PIUs on the assumption that the low-dielectric material concerning the right side of FIG. 5 is adopted as a material of printed circuit boards. The transmission losses are detected as losses in the amplitude of a signal with respect to a difference between the amplitude of a signal transmitted from a transceiver LSI and the sensitivity of a transceiver LSI to a received signal.
As mentioned above, the conventional transmission wiring design systems shown in FIG. 3 are used to design the wiring in the PIU 1, PIU 2, and BWB respectively while the transmission wiring design systems are physically separated from one another and independent of one another. This poses a problem in that the overall operation of a system cannot satisfy a desired standard. Consequently, redesigning of the wiring in the components and subsequent checking of the overall system operation are repeated frequently. This leads to the situation of terribly inefficient development.
FIG. 7 shows an example of a table listing line lengths and delay times that are designed for the components by means of the transmission wiring design systems shown in FIG. 3.
In this example, an addition/drop multiplexer (ADX) is adopted as the PIU 1, and a multiplexer (MUX) is adopted as the PIU 2. In the drawing, group 141 refers to a group of lines 141. The group of lines 141 include line pairs 141A, 141B, 141C, 141C, etc., 141G, and 141H.
Herein, the line lengths and delay times designed independently for the ADM, MUX, and BWB are collected, and it is judged in terms of the overall system operation whether a design for each line pair is acceptable. The results of judgments are also listed. The differences in delay times and total attenuation levels are listed on the right-hand columns of the table. Herein, the “difference in delay time” refers to a difference between delay times occurring on two lines constituting each of the line pairs that form a transmission line extended throughout the system. An effective wavelength of a received differential-mode signal is regarded as the difference in delay time. Moreover, the attenuation level refers to a magnitude of attenuation occurring on each line pair spread throughout the system as shown in FIG. 6.
In the above example, the attenuation levels of the line pairs 141A and 141B are 11.083 and 11.027 (dB) respectively and are larger than those of the others. Therefore, it is judged that the designs for the line pairs are unacceptable (No good).” In this case, attenuation levels to be caused by the ADM, MUX, and BWB are re-calculated. Based on the results of calculation, wiring is redesigned for each of these components. Thus, the results of wiring design performed on the components are collected first, and it is then judged whether the design of each of numerous line pairs is acceptable. If it is judged that the design of each line pair extended throughout the system is unacceptable (No good), the transmission wiring design systems are reused to redesign the wiring in the respective components. The thus complex design process must be followed. This means that development of a BWB system is very inefficient.